1. Field of the Disclosure
The present disclosure relates to semiconductor devices and to a method of forming semiconductor devices, and, more particularly, to field effect transistors in fully depleted silicon-on-insulator technologies at advanced technology nodes, such as 22 nm and beyond.
2. Description of the Related Art
In recent years, lateral double-diffused MOS transistors (LDMOSFETs) have been increasingly applied in high voltage and smart power applications. The advantages over vertical double-diffused MOSFETs (VDMOSFETs) are a reduction in the number of application steps, multiple output capability on the same chip, and compatibility with advanced very large scale integration (VLSI) technologies. LDMOSFETs with VLSI processes are expected to drive ICs to wider fields of complex applications, such as intelligent power ICs. Actually, with the internet of things (IoT) or internet of everything becoming a term that is more and more popular, IoT promises a vast field of application in medical, automotive, industrial, metrology, fitness and more applications. These different applications largely have several requirements in common, such as cost sensitivity, long battery life, and increasingly wireless connectivity. Particularly, the latter requirement of wireless connectivity demands wireless interfaces requiring radio frequency (RF). Recently, a process at 28 nm targeting at IoT in mobile applications has been proposed, this process adding RF modeling to high-K metal gate (HKMG) processes, being designed for devices that require those standby power and long battery life integrated with RF/wireless functionality.
Generally, LDMOSFETs implement an asymmetric structure with a drift region located between the LDMOSFET's channel and drain contact. With regard to FIG. 1a, a schematic cross-section of an LDMOSFET 100a in accordance with bulk technologies is schematically illustrated. The LDMOSFET 100a comprises a bulk substrate 110a having a first well 112a and a second well 114a formed in an upper surface portion of the bulk substrate 110a. The first well 112a and the second well 114a are doped with dopants of opposite conductivity types, i.e., P-type and N-type dopants. Overlying an interface between the first well 112a and the second well 114a, a gate electrode 120a is disposed over the bulk substrate 110a, the gate structure 120a partially covering the upper surface regions of the first well 112a and the second well 114a. The gate structure 120a has a gate stack 122a comprising a gate dielectric (not illustrated) and a gate electrode material (not illustrated). The person skilled in the art will appreciate that the gate dielectric and the gate electrode material, though not explicitly illustrated in FIG. 1a, are formed in accordance with known gate formation techniques, and sidewalls of the gate stack 122a are covered with a sidewall spacer 124a. A source region 132a is provided within the first well 112a in alignment with the gate structure 120a, wherein a lateral distance between the source region 132a and the gate stack 122a is adjusted by means of the sidewall spacer 124a. 
As illustrated in FIG. 1a, a drain region 134a is formed within the second well 114a. The drain region 134a is substantially doped with dopants of the same conductivity type as the second well 114a. A concentration of dopants of the second conductivity type within the drain region 134a is substantially higher than a concentration of dopants of the second conductivity type within the second well 114a. For example, in order to implement an NLDMOSFET, the source and drain regions 132a and 134a are strongly doped with N-type dopants, i.e., the source and drain regions 132a, 134a are N+ regions. The first well 112a is doped with P-type dopants implementing a P-well, while the second well 114a is doped with N-type dopants for forming an N-well.
With regard to FIG. 1a, extension regions and halo regions may be provided within the first well 112a, as indicated by reference numeral 136a, for adjusting the threshold voltage of the LDMOSFET 100a. The gate electrode 120a covers the surface of the channel within the first well 112a and the drift region within the second well 114a. The drift region within the second well 114a being covered by the gate structure 120a extends into a long drift region indicating a spacing between the gate structure 120a and the drain region 134a. Accordingly, the LDMOSFET as illustrated in FIG. 1a has three major serial resistance components in accordance with the channel region in the first well 112a below the gate structure 120a, the drift region within the second well 114a below the gate structure 120a, and the long drift region within the second well 114a extending beyond the gate structure 120a to the drain region 134a. For LDMOSFETs in high voltage applications, the dominant part among these serial resistance components is given by the drift region within the second well 114a below the gate structure 120a and the long drift region within the second well 114a beyond the gate structure 120a to the drain region 134a. Accordingly, for LDMOSFETs in high voltage applications, the dominant part among these serial resistance components is the drift resistance provided by the drift region and the long drift region, receiving the high voltage drop along the LDMOSFET 100a. 
As illustrated in FIG. 1a, a back bias contact region 138a is formed within the first well 112a, the back bias contact region 138a being enclosed by STI regions 142a, 144a separating the back bias contact region 138a and the source region 132a. The back bias contact region 138a is doped with dopants of the same conductivity type as the first well 112a, having a higher concentration of dopants than the first well 112a. Accordingly, the back bias contact region 138a represents a highly doped region 138a within the first well 112a. 
With regard to FIG. 1b, an LDMOSFET 100b is schematically illustrated in a cross-sectional view, the LDMOSFET 100b being formed in accordance with a pure slave FDSOI semiconductor device construction. The term “pure slave” indicates that the LDMOSFET 100b uses technology components, mostly implants, which are already required for by other baseline devices and, therefore, the LDMOSFET 100b is integrated in accordance with processes employed in the baseline for forming semiconductor devices at 28 nm and above. Particularly, the LDMOSFET 100b is not formed by dedicated process features and, therefore, does not require additional mask layers in the process flow.
Although the LDMOSFET 100b is formed in accordance with FDSOI techniques, the LDMOSFET 100b is provided in and above a bulk substrate 110b which is part of an SOT substrate (the term “silicon-on-insulator” or “SOT” indicating a substrate configuration having an active semiconductor layer which is separated from a bulk substrate below by means of an interposed buried oxide (BOX) layer). Particularly, the LDMOSFET 100b is formed within a bulk exposed region of the SOT substrate, that is, a local region of the SOT substrate (not illustrated), where the active semiconductor layer (not illustrated) and the BOX layer (not illustrated) are locally removed to locally expose an upper surface of the underlying bulk substrate 110b. For example, bulk exposed regions or BULEX regions may be formed when implementing back bias in FDSOI technologies, wherein back bias contacts regions are formed adjacent to VDMOSFETs, the back bias contacts being electrically coupled to the BULEX regions.
With regard to FIG. 1b, the bulk substrate 110b has a first well 112b and a second well 114b formed in an upper surface portion of the bulk substrate 110b. The first well 112b and the second well 114b are doped with dopants of opposite conductivity types, i.e., P-type and N-type dopants. Overlying an interface between the first well 112b and the second well 114b, a gate electrode 120b is disposed over the bulk substrate 110b, the gate structure 120b partially covering the upper surface regions of the first well 112b and the second well 114b. Similar to the gate structure 120a, the gate structure 120b has a gate stack 122b comprising a gate dielectric (not illustrated) and a gate electrode material (not illustrated). The person skilled in the art will appreciate that the gate dielectric and the gate electrode material, though not explicitly illustrated in FIG. 1b, are formed in accordance with known gate formation techniques, and sidewalls of the gate stack 122b are covered with a sidewall spacer 124b. 
A source region 132b is provided on the first well 112b in alignment with the gate structure 120b, wherein a lateral distance between the source region 132b and the gate stack 122b is adjusted by means of the sidewall spacer 124b. As opposed to the LDMOSFET 100a, the source region 132b is formed by an epitaxially grown region which is in alignment with the gate stack 122b. 
Furthermore, a drain region 134b is formed on the second well 114b. The drain region 134b is substantially doped with dopants of the same conductivity type as the second well 114b. A concentration of dopants of the second conductivity type within the drain region 134b is substantially higher than a concentration of dopants of the second conductivity type within the second well 114b. The drain region 134b is, as the source region 132b, an epitaxially grown region, which may be formed when growing the source region 132b. 
Similar to the description of FIG. 1a above, an NLDMOSFET may be implemented by the source region 132b and the drain region 134b being strongly doped with N-type dopants, i.e., the source region 132b and the drain region 134b are N+ regions. In case the first well 112b is doped with P-type dopants implementing a P-well, the second well 114b is doped with N-type dopants for forming an N-well.
Similar to FIG. 1a above, a back bias contact region 138b is formed within the first well 112b, the back bias contact region 138b being laterally enclosed by STI regions 142b, 144b separating the back bias contact region 138b and the source region 132b. The back bias contact region 138b is doped with dopants of the same conductivity type as the first well 112b, having a higher concentration of dopants than the first well 112b. The back bias contact region 138b represents a highly doped region 138b formed on the first well 112b as an epitaxially grown region. An STI region 146b separates the drain region 134b and the gate structure 120b. 
FIG. 1b shows a direct port of an LDMOS design of bulk technologies to FDSOI technologies, that is, the fabrication of LDMOSFET devices as described above with regard to FIG. 1a is directly transferred into FDSOI process flows as pure slave LDMOS devices.
Irrespective of the type of LDMOSFET, that is, the LDMOSFET 100a or the LDMOSFET 100b, the integration of pure slave LDMOSFETs makes extensive use of logic device construction elements, such as forming well regions in the device body, forming of complementary well regions for the drain drift region and the formation of source/drain regions, either by implanting the source/drain regions or epitaxially growing source/drain regions.
The major difference in LDMOSFET 100b with respect to LDMOSFET 100a, however, is the absence of extension and halo regions, because they are not required for baseline SOI devices. It turns out that, upon employing bulk and FDSOI techniques in slave LDMOS process flows, body/drain extension implants (wells 112b and 114b) may cause a very high threshold voltage, a very high subthreshold slope, and a strong hot carrier injection (HCI). The root cause is the high surface dopant concentration in the FDSOI wells. They are intended as backgates for the SOI devices and need to be highly doped to avoid gate depletion effects.
Furthermore, the formation of source/drain connections causes a degraded source/channel connection, which cannot be cured by implanting extensions.
In view of the above discussion, it is desirable to provide a semiconductor device and a method improving source/channel connection and reducing the threshold voltage, as well as the subthreshold slope and improving HCI.